1. Field of the Invention
The present invention relates to a wafer testing apparatus, and more particularly, to a probe card where more number of testing probes can be disposed thereon by modifying the layout of the circuit board.
2. Description of Related Art
Along with progressive development of the semiconductor fabricating process, the channel length of the modern semiconductor process is reduced from 0.15 μm to 0.13 μm and further to the newest 90 nanometer. During the semiconductor fabricating process, in order to ensure the yield rate and avoid the package wastage, the electrical properties and the functions of the wafer are required to be tested before the wafer is fabricated, cut and packaged. In such testing method, a testing loop is constituted by a test tool and a probe card, and each probe pin on the probe card directly contacts a pad or a bump on the chip, such that a chip signal is extracted from each chip on the wafer through the probe. Thereafter, the chip signal is sent to the test tool for further analysis. With such testing method, the chips with poor electrical properties or functions are scrapped before the wafer is packaged, such that the problem of the package fabricating cost increasing due to the growing number of the wafers with poor quality is effectively eliminated.
FIG. 1 schematically shows a layout diagram of a conventional probe card. Wherein, the probe card 100 includes a front surface and a back surface that have the specific layout and arrangement as shown in FIGS. 1(a) and 1(b), respectively. Referring to FIG. 1(a), the front surface of the probe card 100 includes multiple pogo pads 120, multiple capacitors 130, and multiple relays 140 that are disposed on the circular printed circuit board (PCB) 110. Wherein, the pogo pads 120 are disposed on the periphery of the PCB 110 with a ring arrangement aligned to the center of the PCB 110. The capacitors 130 and the relays 140 are disposed outside a square area aligned to the center of the PCB 100. Referring to FIG. 1(b), the back surface of the probe card 100 includes a square ceramic head 150 that is disposed on the circular PCB 110. In addition, multiple probe pins 160 are disposed on the ceramic head 150 with an arrangement of a square-shaped array.
The connection and function of the tester are described in detail hereinafter. Wherein, the pogo pads 120 are connected to multiple pogo pins (not shown) on the mother board of the test tool, such that the test signal is transmitted from the mother board to the probe pins through the pogo pads 120, and then the test signal is further transmitted to multiple chips of a test wafer for performing a functional test. In addition, the relays 140 are cooperated with the capacitors 130, such that the capacitors 130 can be controlled and switched by the relays 140 according to the instruction of the test signal to filter the noise in the test signal.
However, since the ICs currently used are demanded to be smaller and capable of providing more functions and higher pin counts, under the pressure of the successful development of the driver share testing method, more number of probe pins are demanded by the test tool. However, the number of the probe pins used in the present probe card is not changed, if the conventional probe card is used to test the wafer, it may require more time and more effort, and the lifespan of the probe card is significantly impacted due to the over-worn of the probe pin. In addition, if it is required to add more number of probe pins on the probe card, since the space on the probe card is limited, the probe card cannot accommodate all of the testers. Moreover, if the size of the probe card is needed to be enlarged, both of the securing unit of the mother board and the probe card of the test tool have to be redesigned and modified accordingly, which significantly raises the test cost.